1. Field of the Invention
The invention relates to the field of MOS computers, U.S. Class 340/172.5.
2. Prior Art
General purpose digital computers employing a plurality of MOS chips such as a CPU chip, random-access-memory (RAM) chips and read-only-memory (ROM) chips are known in the prior art. For example, see U.S. Pat. No. 3,821,715.
It is often desirable to know the status of the CPU, for example, whether it is halted or communicating with an input/output bus or a plurality of other conditions. Such status determinations are well known in the prior art. As will be discussed in more detail in conjunction with FIG. 1 which shows a portion of the circuitry of the 8008 Microprocessor marketed by Intel Corporation in March, 1972 and described in Section 2 -- Processor Timing and Section 5 -- Processor Control Signal of the MCS-8 User Manual therefor, in the prior art (particularly in a multi-chip MOS computer) in order to determine the status of the CPU, an encoded signal is generated by the CPU and communicated to a decoder. The encoded signal is then decoded by the decoder resulting in a CPU status signal such as halted, input/output, etc. The encoded CPU status signal required that a plurality of lines be used to communicate the status from the CPU to the decoder. This plurality of lines required additional pin connections to the CPU chip. In the fabrication of an MOS computer these additional pin connections to the CPU are burdensome, costly or may require the use of pins needed to perform other functions. As will be seen, the present invention eliminates the need for the pins associated with the encoded processor status signal.
Again, as will be discussed more fully in conjunction with FIG. 1, a special instruction or jump instruction is often utilized in prior art computers. This instruction, by way of example, may be inserted into the computer, by an operator, through a manual push-button, and may be used to cause the CPU to jump to some predetermined instruction. Further, by way of example, the jump instruction may be used to restart the program. In the prior art, circuitry which often utilized logic components, such as gates, generated the jump instruction. As will be seen in the present invention, the jump instruction is, in effect, the lack of any instruction, that is, all zeroes or all ones, and may be generated by inhibiting the communication of an instruction from a memory to the CPU in a multi-chip MOS computer by, for example, either grounding all the data bus lines or applying a signal representative of a binary one to all the lines.